The following example illustrates the introduction of PIN diode into WIPL-D Microwave schematic through the design of single pole double throw (SPDT) switch utilizing two PIN diodes. The diodes are represented in a form of an equivalent circuit. Due to the operating principle of the switch, both ON and OFF equivalent circuits are used in the same circuit.

Schematic of the switch is shown in Fig. 1. The requirement for such a switch is to route a signal applied to an input port (port 1) to one of the other two output ports (port 2) while the remaining output port (port 3) should remain isolated. The switching function is provided by connecting the isolated output port to a ground through a low impedance of a PIN diode when it is biased in ON state. To provide direct signal path, the PIN diode at the other output port should be biased in OFF state providing high shunt impedance which doesn’t significantly influence the loss of the direct transmission path. To reverse the direct transmission path from port 2 to port 3, the bias of the diodes should be switched. Quarter wavelength transformers are introduced to connect both PIN diodes to the input port in order to prevent a short circuited diode to load the input port.

The same switch can be utilized in the case when an application scenario requires the directions of the signals in the switch to be altered providing the alternative connection of one of the two input signals (at ports 2 and 3) to the output port (1).

The transmission S parameters for the direct and isolated transmission paths are shown in Fig. 2. Within the frequency band of interest (±10%) the isolation is in the range of approximately 12-14 dB.

Such isolation values are illustrative to explain the principle of switch operation, which is particularly good example to demonstrate the introduction of semiconductor devices in circuit simulation, but are perhaps not sufficient for practical applications. The first step to obtain more practical values in the range 20-25 dB would be to replace quarter wavelength transmission line segments with more complex networks.

In the scope of a previous paragraph, a topology for reasonable small signal model given by a manufacturer for a packaged GaAs High Electron Mobility Transistor (HEMT) is presented in Fig. 1.

The model consists of 16 elements. The elements used to model the internal structure of the transistor within a semiconductor die are usually called intrinsic elements. The other elements, used to model the influence of a package to the transistor performance, are called extrinsic elements, or simply package parasitics. Intrinsic elements are bias dependent while the extrinsic are not. The list of the intrinsic and extrinsic elements from Fig. 1 is presented in Table 1.

Package parasitics include resistances (Rg, Rs, Rd) and inductances (Lg, Ls, Ld) of transistor gate, source and drain leads respectively. A transistor package adds parasitic capacitances between the electrodes (Cpgs, Cpds, Cpgd). Capacitance between gate and source (Cgs) is bias dependent. Large input transistor resistance in parallel to the capacitance Cgs is modeled with 1 MΩ resistor. Voltage across the input resistance is a control voltage for the current generator in the drain. The transconductance of this generator is Gm and the delay of drain current with respect to the control voltage is Tau. Drain current drives a parallel connection of the resistance Rds and capacitance Cds. A parasitic capacitance between gate and drain has a value Cgd.

To systematically examine the influence of a biasing point to transistor characteristics in WIPL-D Microwave, it is convenient to specify values for extrinsic elements in the schematic, and to define values of intrinsic elements as symbols. In such a way a change of biasing point can be easily accommodated by changing values for the symbols, as presented in Fig. 2.

Average Measured S Parameters vs.
S Parameters Calculated using Model

For a particular transistor selected for illustration of model implementation in WIPL-D Microwave, equivalent circuit model elements are listed for four Vds values, 1.5, 2.0, 3.0 and 4.0 V, with Ids spanning values of 5, 10, 15 and 20 mA. Average measured S parameters are provided for drain current Ids=20 mA at the same values of drain to source voltages. This allows for direct comparison between the two means of S parameter calculations.

The comparison of S11 and S22 is presented in Fig. 3 using Smith chart format for simultaneous comparison of magnitude and phase. The S parameters calculated using model from Fig. 1 (blue traces) are in excellent agreement with average measured data (red traces). S21 and S12 are not presented in the figure due to the very high and very low magnitude values respectively which is not effectively visualized in the Smith chart format. The minor discrepancy between a model and an average device performance comes from the limitations of the relatively simple model from Fig. 1 to take into account all the features affecting the transistor performance. However, the discrepancy can be neglected for practical designs. This can be easily justified as the spread in the characteristics from one device to another, also provided by a manufacturer, is larger. For an example, the spread in transistor gain at 12 GHz is larger than 1 dB.

The results presented in Fig. 3 illustrate the importance of accurate modeling of the transistor as noticeable variations of S parameters occur for different bias points. Changes of Cgs and Rs as Vds varies do not affect significantly values of S11, while variations of S22 due to the changes in values of Rds are more obvious.

As the S parameters calculated using the transistor model match up well with the S parameters obtained by measurements, the model can be used to explore transistor performance for the case where a list of measured S parameters is not available, e.g. to quantify the influence of Ids to S21. The intrinsic model parameters for four Ids values corresponding to the drain-source voltage Vds=2V are presented in Fig. 4. The results of S21 simulations in WIPL-D Microwave are presented in Fig. 5. As expected, the S21 values increase as Ids increases. The dominant effect leading to an increase is the change in Gm, as can be clearly seen from values highlighted in Fig. 4.

Conclusion

The accurate transistor characterization is a starting point to carry out an amplifier design. Lumped circuit equivalent transistor models are compact and versatile means of providing reliable S parameter data. WIPL-D Microwave provides a complete environment to implement these models.

The modeling of a commercially available low power packaged GaAs HEMT has been illustrated. The partitioning of the transistor equivalent circuit to intrinsic and extrinsic elements has been presented and physical grounds behind each of the elements explained in brief. It has been shown that S parameters calculated using the model are highly accurate and can be utilized to overcome the limitation imposed with sparsely tabulated transistor data, e.g. to find the optimal biasing point for a desired application.

For some other transistor technology, perhaps an equivalent circuit topology different from the one presented in Fig. 1 will be adequate for modeling. WIPL-D Microwave design environment provides required flexibility to implement a schematic of any commonly used linear transistor model.

Unpackaged (bare die) devices are usually utilized along with an interconnection technology that is not known by a transistor manufacturer, and equivalent circuits provided usually contain only intrinsic elements. In that case, for an accurate design, a user should use electromagnetic (EM) simulations to model accurately model the influence of an interconnecting technology to transistor performance. More details how to perform EM simulations for the specific case of bond wire connections can be found in the application note “Bond Wires as an Interconnect Technology” available for download from WIPL-D web site.