Modeling of Microstrip Circuits
6-Way Divider – Modeling
and Analyzing in WIPL-D Pro
Matching Network Design
for Power Amplifiers
Power Detector with aZero-Bias Schottky Diode
Wilkinson Combiner/Dividerat High MW Frequencies
6-Way Divider – Modeling and Analyzing in WIPL-D Pro
In this application, we will analyze 6-way divider. The divider will be simulated from 1.4 GHz to 1.6 GHz. The results of interest will be s11, s21, s31… s71 parameters.
Feeding port is marked using number 1 while other 6 ports are marked using numbers 2-7. The divider is fed by probe with SMA connector (Figure 2).
Figure 1. Layout of the divider.
Figure 2. SMA connector on the first port.
Figure 3. Table of symbols.
In WIPL-D, there are procedures for modeling the divider:
- by using WIPL-D own tool (defining symbols, nodes, creating plates…)
- by using WIPL-D own tool (defining symbols, grids; creating plates…)
- by using AW Modeler for importing .dxf file
- by using WIPL-D Pro CAD for importing .x_t, .stp, .sat, .iges…
The first procedure will be presented in this paper. It is very simple, but it takes a bit more time than the other procedures. Nevertheless, with this procedure we can obtain optimal mesh and minimize simulation time.
All dimensions are given using symbols. Table of symbols is presented in Figure 3.
Layout of the Wipl-D model and clarifications of some symbols are shown in Figure 4.
Figure 4. Layout of Wipl-D model.
Feeder on the port 1 is modeled as coaxial line using Wipl-D objects (BoR and Circle). Specifications of BoR and Circle objects are presented in Figures 5-6.
Figure 5. Specification of a BoR object.
Figure 6. Specification of Circle object.
Feeder attached to the first port is shown in the Figure 7.
Feeders on the other ports (ports 2-7) are the same. Model of this feeder is shown in Figure 8.
Figure 7. Coaxial feeder on the first port.
Figure 8. Feeder on the port 2.
Frequency range mentioned above (1.4 GHz to 1.6 GHz) was divided into 11 frequency points. Operation mode ANTENNA (One generator at time) is chosen.
As we can see from Figure 1 and Figure 3, model is symmetrical versus x0z plane. Anyway, we simulated the whole model.
Table 1. Simulation time and number of unknowns.
|Simulation time per frequency||Number of unknowns|
The simulation was carried out on Intel® Core™ 2 Quad 64 bit processor (2.66 GHz) with 4 GB of RAM. The tool used for simulation is WIPL-D Pro on Windows XP platform.
Magnitude of s11 (in dB) parameters is shown in Figure 9.
Figure 9. Magnitude of S11 parameters.
Results for the other parameters of interest are shown in Figures 10-11. Because of symmetry of the structure, parameters s21 and s31, s41 and s51 and finally, pair of s61 and s71 are with the same values. Thus, only parameters s21, s41 and s61 are displayed here.
Figure 10a. Parameter s21 – magnitude.
Figure 10b. Parameter s11 – phase.
Figure 11a. Parameter s41 – magnitude.
Figure 11b. Parameter s41 – phase.
Figure 12a. Parameter s61 – magnitude.
Figure 12b. Parameter s41 – phase.
If you have a specific problem in mind and you are not sure if WIPL-D software can handle that problem, contact us. We will analyze your needs and try to help, and if our products satisfy your requirements, we will make you the best possible offer for purchase.
Matching Network Design for Power Amplifiers
Discrete, general purpose microwave transistors are usually accompanied with an extensive set of data supplied by a manufacturer to support versatile designs of many active circuits such as linear and low noise amplifiers, oscillators, frequency multipliers and mixers. A basic data set typically includes an I V curve and a list of small signal S parameters and noise parameters vs. frequency for several biasing points. These data are sufficient to carry out linear and low noise amplifier design using linear circuit simulator. In relation to amplifiers, transistor data sheets usually contain some additional nonlinear parameters such as level of third order intermodulation products (IP3) and gain compression (P1dB) only to indicate operational boundaries for a device.
For accurate design of strongly nonlinear microwave circuits, such as oscillators or frequency multipliers, use of nonlinear time domain or harmonic balance simulators is required. Modeling a device for use in nonlinear simulators is significantly more complex than providing a list of linear S parameters. This kind of model is usually a result of comprehensive procedures of advanced experimental characterization followed by nonlinear model parameter extraction. Sometimes a nonlinear model suitable for direct implementation in nonlinear circuit simulators is additionally provided in the transistor datasheets.
A class of strongly nonlinear circuits that are, in spite of a high level of maturity of nonlinear modeling and simulation tools, still designed using linear techniques, are power amplifiers. The reason for this approach can be found in a fact that requirements for modern power amplifiers are numerous, stringent and usually conflicting each other. Conditions of operation providing maximum output power, power gain, and power added efficiency (PAE), acceptable level of nonlinear distortion and memory effects for an input signal with prescribed modulation, peak-to-average power ratio (PAPR), and envelope statistics, are still too demanding for state of the art nonlinear modeling and simulation methodologies. Furthermore, a set of requirements for a power amplifier has resulted in a situation that a power transistor itself is designed for a particular application only. In other words, in contrast to general purpose transistors, a number of application scenarios for a typical power transistor is usually only one. For the scenario, in most of the cases, the optimum operating conditions are best determined experimentally using very complex and expensive setup that is beyond the reach of a typical designer. Data describing the optimum operating condition for a device is usually provided by a manufacturer. Sometimes a transistor manufacturer even discloses the design of an amplifier circuit including printed circuit board (PCB) layout and a bill of material (BOM) for the components used.
It seems like a designer can only choose a device which suits the application scenario and strictly follow the manufacturer’s recommendations. However, there is still some flexibility for a power amplifier designer to verify a recommended design before prototyping and make changes if necessary, or to adapt it to some specific circumstances, for example when a different substrate material is preferred. This application note describes how to carry out a reliable power amplifier design using WIPL-D Microwave.
Example of Typical Power Transistor Data
Table 1. Optimal source and load impedances supplied by a manufacturer for a particular RF power transistor.
|f [MHz]||Zsource [Ω]||Zload [Ω]|
|2500||4.059 - j2.284||3.380 - j0.543|
|2525||3.679 - j2.593||3.265 - j0.546|
|2550||3.006 - j2.574||3.077 - j0.449|
|2575||2.355 - j2.190||2.892 - j0.336|
|2600||2.075 - j1.657||2.727 - j0.182|
|2625||1.930 - j1.179||2.564 - j0.034|
|2650||1.973 - j0.771||2.435 + j0.140|
|2675||2.017 - j0.557||2.286 + j0.340|
|2700||2.024 - j0.379||2.227 + j0.538|
Data supplied by power transistor manufacturers include a list of optimal impedances vs. frequency that should be presented at transistor input and output electrodes to ensure the specified performance for a targeted application. As pointed out earlier, these impedances are determined using complex procedures and sophisticated measurement equipment.
An example of a data set provided for a transistor suitable for 2.5-2.7 GHz frequency band, thus addressing WiMAX, WiBro, BWA and multicarrier OFDM applications and operating in Class AB or Class C, is presented in Table 1. Impedance Zsource represent an optimum impedance to be presented at the gate of the MOSFET at a given frequency, while Zload represent the impedance to be presented at the drain.
Analizing data listed in Table 1., it can be concluded that values of the impedances are very low, and therefore a design of the matching networks is not a trivial task. The flexibility given to a designer, and in the same time a challenge, is to design adequate matching networks that will transform the reference impedances of the amplifier within a system (50 Ω) to the required optimum values at the transistor terminals.
Figure 1. Optimum source and load impedances added as schematicentities through Touchstone Z parameter Data block and graphedon a Smith chart in WIPL-D Microwave.
In order to carry out a design of matching networks using WIPL D Microwave, the optimum impedances can be introduced in the simualtor environment through Touchstone Z parameter data block, as presented in Fig.1.
Matching Network Consideration
There are many ways to match an impedance in a given frequency band. Different topologies utilizing lumped elements, transmission lines or both are possible. The selection of a topology utilized for a particular application depends on many factors.
For amplifiers in general, matching networks must provide DC paths for biasing an active element. Furthermore, a topology chosen should include elements to decouple the amplifier terminating lines from a flow of DC biasing currents, and DC biasing terminals from flow of RF currents. The former is typically realized as a pair of parallel coupled transmission lines which are quarter wavelength long at the operating frequency, or a series capacitor. The latter is especially important to keep the amplifier stable. It is usually realized as a shunt short circuited stub which is quarter wavelength long at the operating frequency, or a shunt inductor. Shunt short stub at the operating frequency represents an open circuit, and therefore doesn’t load the rest of the matching network. For the same reason, a properly dimensioned inductor should have sufficiently high impedance at the operating frequency.
In the case of a power amplifier, a subtle detail could prevail in the choice of a suitable matching network topology. For an example, harmonic content of a signal coming out from a power amplifier is very important for a number of applications. In that sense, it becomes important if the output biasing network contains a shunt short circuited stub or an inductor. In principle, at second harmonic of the operating frequency, the stub will ideally act as a short circuit, therefore preventing the signal to flow to the output of an amplifier. The impedance of an inductor will be two times higher than the one at the operating frequency, which could be insufficient to completely block the second harmonic signal. Furthermore, practical inductors with high inductance values required at operating frequency typically have low self-resonant frequency, which may easily fall below the second harmonic, making the behavior of an inductor at the second harmonic frequency unpredictable.
For the particular case of the power transistor described, the schematics of both matching networks as recommended from a manufacturer are presented in Fig. 1. Only the elements critical for high frequency operation are considered. Both networks consist of a combination of lumped and transmission line elements. In input network resistor R1 is used as a matching element together with a quarter wavelength, high impedance biasing line effectively short circuited at the other end by a capacitor C2. The purpose of the capacitor C1 is to isolate the input port for DC currents.
Similarly, capacitor C1 in output matching network prevents the flow of DC currents through the output port. Biasing is again introduced using two shunt high impedance lines that are approximately quarter wavelength long and short circuited for microwave signal through the capacitors C2 and C3. According to the manufacturer’s recommendations, two biasing lines with slightly different lengths should be used. The reason for this is to widen a bandwidth of aforementioned second harmonic suppression. If the lengths of both lines were the same, this would result in a sufficiently high value of harmonic suppression occurring at the single frequency.
As shown in Fig. 2, both matching networks have a part comprising transmission line elements, which are illustrated in Fig. 3. Actually, the representation shown in Fig. 3 corresponds to the models of the matching networks implemented in WIPL D Microwave by using electromagnetic (EM) components. The significance of introducing EM components for most accurate modeling of microstrip matching elements will become apparent in the following text.
Figure 2. Schematics of input and output matching networks as suggested by a manufacturer in WIPL-D Microwave.
The thickness of a microstrip substrate used is dictated by a physical location of transistor leads with respect to the bottom of the transistor capsule. At the place of transistor mounting, a cutout in a substrate must be made to allow the direct attachment of the source electrode, which is electrically connected to the bottom of the transistor housing, to the metal supporting plate acting as a ground and providing thermal path for effective cooling of the device.
The width of the transistor leads on gate and drain side is substantial, approximate ratio to the other elements of matching networks is illustrated in Fig. 3. The substantial lead width determines the minimum transmission line width to be used for a first transmission line matching element in both of the networks. However, wide leads conform well to the low values of the optimum impedances to be presented to the device at both terminals, as low impedance microstrip transmission line sections are required for the first matching element in the networks, which directly translates into substantial line widths.
Figure 3. WIPL-D EM component models of transmission line parts of input and output matching networks.
Both of the transmission line networks have similar topology. In input matching network, the first transmission line element is an impedance transformer. It is wider that the lead of the transistor which effectively creates a discontinuity that must be taken into account. On the other hand, the first matching element in drain circuit utilizes a triple step to gradually increase of line width to realize an impedance transformer. The second matching element in both of the networks is very narrow, very short transmission line which is electrically equivalent to an inductance. Extremely high ratio of line width change (approximately 1:20 for the case of gate matching network) significantly contributes to an inductance value and must be accurately taken into account. The third element in the matching networks is a short, low impedance transmission line section acting as an impedance transformer. In the input network a transformer is tapered at one end. Finally, both networks end with a piece of a 50 Ω transmission line. Locations of the connections of distributed and lumped elements from Fig. 2 comprising matching, DC biasing and DC blocking circuits are also indicated in Fig. 3.
WIPL-D Microwave has several built-in technology libraries with circuit element models of commonly encountered transmission line discontinuities. The user can choose weather the calculations of electrical characteristics of a discontinuity will be based on approximate analytical expressions or full wave EM simulations. The accuracy of the analytical expressions is in a practically acceptable range of several percent for the case of mild discontinuities. However, the accuracy becomes unacceptable for connection of two, three or four lines with drastically different widths, such is the case for some of the discontinuities presented in Fig. 3. To obtain accurate results for such extreme case, an electromagnetic simulator must be used. However, as evident from Fig. 3, discontinuities are physically located very close to each other. When this is the case, discontinuities are said to be coupled. The coupling between the discontinuities introduces additional effects comparing with the case where the coupling does not exist. A circuit comprising coupled discontinuities can not be accurately modeled as if the discontinuities were not coupled. Therefore, for the case of matching networks from Fig. 3, neither the analysis with analytic models nor the analysis utilizing EM modeling for each of the individual discontinuity is adequate.
On the other hand, each network includes long and uniform transmission line segments, such as terminating and biasing lines, which can be efficiently modeled using analytic component models. An interface between the “analytic” and “electromagnetic” part of the circuit, and connections between transmission lines and lumped elements can be accurately modeled in WIPL-D Microwave by proper alignment of the reference planes on interconnecting ports, as illustrated in Fig. 3, and the use of de-embedding.
Figure 4. Simulated performance of input matching network usingmodeling and optimization options available in WIPL D Microwave.
The possibility to partition the circuit as presented in Fig. 2, i.e. introducing analytical elements where appropriate, and EM components where coupled discontinuities require EM analysis within a single design environment, makes WIPL-D Microwave a tool of choice for power amplifier design. A built in optimizer can be used for subsequent optimization of all of the elements of a network including EM component elements and optimum dimensions of microstrip circuits can be easily determined.
An outline of the optimum design flow for the previously presented power amplifier is presented next. As a first step, circuit models for each of the matching networks using analytic components only have been assembled in WIPL D Microwave. Dimensions of the microstrip elements have been optimized to give return loss value better than 15 dB at the central frequency of operation (2.6 GHz). The simulated S parameters of all-analytic models of the networks are shown in Fig. 4-5.
Figure 5. Simulated performance of output matching network usingmodeling and optimization options available in WIPL-D Microwave.
More accurate modeling in the next design step should account for the coupling between all of the discontinuities. The simulation of partitioned matching networks according to Fig. 2 gives substantially different results from all-analytic solutions. While the performance of the input matching network can be considered acceptable as the return loss maximum is only slightly shifted to higher frequencies, the performance of the output matching network is not, as it provides around 3 dB return loss within the band. The difference between the results obtained with two modeling approaches best illustrates the limitations of individual modeling of discontinuities when a typical power amplifier matching networks are concerned.
In order to achieve the acceptable values of the return loss for the matching networks, optimization of the schematics shown in Fig. 2 has been performed as the final design step. During optimization only the dimensions of the transmission line elements presented in Fig. 3 have been varied. As a result of optimization, the values for the return loss better than 15 dB have been obtained at the central operating frequency, as presented in Fig. 4-5.
The adequate modeling of matching networks is crucial for the success of power amplifier design. Due to a set of simulation tools included, WIPL-D Microwave provides a complete environment for accurate and efficient modeling and design of power amplifiers.
Example of a comercially available power transistor has been presented to explain the matching network topologies prefered for the power amplifier application and to demonstrate the outline of the complete design flow. The neccessity to introduce electromagnetic analysis to accurately model typical power amplifier matching networks or otherwise face the significant inaccuracy due to the effects of coupled discontinuities has also been explain.
The design has been carried out for the microstrip substrate recommended by a manufacturer. If necessary, it can be easily adapted to any other substrate prefered providing that the substrate thickness conforms with the height of the transistor lead and the first transmission line element in the networks remains wider than the width of the transistor lead.
If you have a specific problem in mind and you are not sure if WIPL-D software can handle that problem, contact us. We will analyze your needs and try to help, and if our products satisfy your requirements, we will make you the best possible offer for purchase.
Design of a Power Detector with a Zero-Bias Schottky Diode
A power detector is an important part of many microwave systems. For an example, it is frequently used in transmitter systems to monitor a power coming out from a power amplifier. If connected in a loop with a variable attenuator and control logic circuit, the power of the amplifier can be adjusted to a required level. At the receiver side, a power detector can be used in several ways. In channelized receivers, comprising a battery of narrowband filters, a power detector can be placed at each filter output allowing instantaneous monitoring of the spectrum with a resolution of a filter cell in the frequency span of the battery. Furthermore, along with the increased interest in researching the possibilities for simplifying transceivers, implementation of power detectors has reemerged. The most promising solution, the so-called six-port topology, utilizes power detectors at the receiver side to replace classical method of signal down-conversion to baseband using a mixer.
This application note describes some practical aspects of designing a power detector with a zero-bias Schottky diode for various applications using WIPL-D Microwave design environment.
Design of a Non-matched Detector
The simplest way to design a detector is to utilize a zero-bias diode, place it on the 50 Ω transmission line, and provide adequate paths and short circuits for DC and RF currents. A zero bias diode does not require any external bias to operate as a detector, and for number of applications non-matched design is adequate. Example of a non-matched detector will be presented for the center frequency of 24 GHz and span of 250 MHz. A dielectric substrate selected for the design has a relative dielectric constant εr=3.5, and thickness h=0.254 mm.
A schematic representing a non-matched detector is presented in Fig. 1. Lumped elements are used to model a diode. Resistor Rs=10.3 Ω models a series diode resistance. A capacitance Cj=0.13 pF arises from the capacitance of a diode junction, while resistance Rj models junction resistance. For zero-bias diodes, junction resistance has a very high value and can be excluded from the schematic. However, many detector diodes are used with a bias and in that case the influence of Rj must be considered. Diode is grounded on the cathode side for a microwave signal.
Figure 1. Schematic of the non-matched power detector using analyticalmicrostrip elements from WIPL-D Microwave library.
Figure 2. Microstrip layout of non-matched power detector automaticallygenerated from a circuit schematic.
Figure 3. S parameters of the schematic from Fig. 1.
Schematic from Fig. 1, where analytical models have been used to model microstrip elements, is very simple as matching is not required. The short taper is used as an interface for adjusting relatively narrow line used to connect the leads of the diode to a terminal 50 Ω microstrip line. Between the taper and the circuit port, a shunt quarter wavelength long transmission line is connected with both, a radial stub and short circuit to ground connected at the other end. A radial stub is basically a wideband capacitance to the microstrip ground. Accordingly, it represents a short circuit for a microwave signal which transforms into open at the connection with the terminal line. Therefore, the terminal line is not loaded by the presence of the short. As indicated, in parallel to the capacitive connection to the ground for a microwave signal, a conductive connection to the ground must be made to allow flow of detected DC current through the diode. This physical connection is conveniently made by using a via (plated through hole). However, at microwave frequencies, the parasitic inductance of via results in a relatively high reactance and performance of via connection to microstrip ground significantly deviates from a short circuit for a microwave signal making pairing with a radial stub necessary.
Microstrip layout of non-matched power detector is shown in Fig. 2. It has been generated as an electromagnetic (EM) component directly from a schematic similar to that from Fig. 1 with a single mouse click using a powerful schematic export to 3D EM Model feature available in WIPL-D Microwave. The only adjustment to the schematic a user has to make involves removing the schematic representation of Rs, Cj, Rj and ideal connections to ground, as these schematic elements do not have adequate layout representation.
The layout shown in Fig. 2 is for illustration purposes only as it is not necessary to introduce an EM component to accurately model the circuit from Fig. 1. For such a simple circuit calculations using analytical microstrip models are sufficiently accurate. Calculated values of return loss of the non-matched detector circuit are presented in Fig. 3. A value of the return loss is approximately 2 dB in the frequency band 22-26 GHz.
Figure 4. Diode reflection coefficient.
Figure 5. Lumped element matching circuit.
Figure 6. Comparison of simulated S parameters for detector schematicsfrom Fig. 5, Fig7 and Fig 9.
Figure 7. Microstrip element matching circuit.
When a detector with such a high return loss value is used in a transmitter power control loop, it is preceded by a directional coupler with a typical coupling coefficient value in the range of 20 dB, or less. Due to the loose coupling, high return loss of a non-matched detector does not affect the performance of the amplifier, or a transmitter chain as a whole.
Design of a Matched Detector
In applications where a detector is used after a filter or connected at the ports of a six-port receiver, a high level of return loss has significant effect, as the performance of these circuits is very sensitive to a value of the impedance presented at the terminals. For such applications, a good match of power detector is essential. The location of diode reflection coefficient in the Smith chart is shown in Fig. 4.
A simple matching network should be used to match the diode or otherwise the insertion loss introduced by the network may affect the sensitivity of the detector. An example of such a network comprising only two lumped elements is presented in Fig. 5. The schematics also contain a transmission line to model the diode pad effect, which is not negligible at the frequency of interest. The recommended pad size is indicated in the figure. The simulated return loss with the lumped elements values optimized is displayed in Fig. 6. Return loss values are significantly improved comparing to the non-matched case reaching a maximum of approximately 15 dB at 24 GHz.
Matching with lumped elements is not adequate at such a high frequency of operation. A network comprising distributed elements should be used instead. One possible solution is to replace L-C matching section from Fig. 5 with a series and a shunt transmission line, as shown in Fig. 7 where a complete microstrip schematic of the matched detector is presented.
Looking from the anode, the first matching element is a short transmission line with the line width set to be equal to diode pad width, so that no discontinuity is introduced. The diode pad line has a characteristic impedance of 69 Ω and replaces an inductor from Fig. 5. Next element in the network is a T-junction connecting together diode pad line, a shunt low impedance line replacing the capacitor from Fig. 5, and 50 Ω terminal line. Low impedance line (20 Ω) is open circuited at the opposite end which is adequately modeled by introducing an open end schematic microstrip element. Last element in the network is shunt circuit comprising quarter wavelength high impedance line (106 Ω), radial stub and via to ensure the flow of DC current trough the diode. The only difference from the previously explained case is that a perfect ground connection from Fig. 1 has been replaced with a via model. Similarly, ideal connection to the ground at diode cathode from Fig. 1 has been replaced with a radial stub, as the short circuit to ground is required there at microwave frequencies only.
Results of the simulation of the schematic from Fig. 7 are presented in Fig. 6. Around 24 GHz return loss values are better than 15 dB. However, the return loss curve is very steep around the minimum indicating that an error in circuit dimensions during fabrication or a variation of diode equivalent circuit parameters from one sample to another may cause a shift of the minimum to other frequency.
Figure 8. A complete layout of the matched detector.
Figure 9. Final WIPL-D Microwave schematic of the matched power detectorincluding all the elements significant at microwave frequencies.
The accuracy of analytical element used to model microstrip T-junction comprising a connection of lines with considerably different widths, such is the case of the one connecting 69 Ω impedance line and 20 Ω line, is poor. Therefore, EM modeling of diode matching circuit is highly recommended. As explained earlier, generation of complete EM component representing the layout of the whole matching network is straightforward in WIPL-D Microwave - the program automatically translates analytical elements into an EM component, as presented in Fig. 8. The figure illustrates the complete matched detector microstrip circuit and indicates the locations of short circuits at DC and microwave frequencies. The layout of a radial stub at diode cathode, which is not a part of designed matching network, is also included. Resistor R and capacitor C are external components which must be added in a real detector circuit, but are not relevant for high frequency simulations. Resistance value should be dimensioned to ensure efficient power transfer of the detected signal to an external circuit. It is usually set equal to the video impedance of the diode (the impedance of the diode as a baseband signal source). Capacitance C is selected according to the required frequency bandwidth of the detected signal and prevents the noise outside the band to affect detector sensitivity.
Optimization of the matching network EM component with the other elements of the detector circuit connected is required to finish power detector design. All of the elements have been assembled in a schematic presented in Fig. 9. The return loss of the optimized circuit is presented in Fig. 6. The values around the frequency of 24 GHz are in the range of 10 dB. The minimum is not as steep as in the case of schematic from Fig. 7 indicating improved sensitivity to fabrication tolerances and the spread of diode characteristics. However, a value of 10 dB may not be sufficient for some applications, e.g. where a filter is connected to detector input.
The design of a power detector can be easily acomplished if the right set of tools is available. WIPL-D Microwave is a one stop design environment providing a microwave circuit designer with several modeling options. The modeling using analytical elements can be smoothly expanded to EM analysis as an automated transfer of any schematic comprising elements with adequate layout representation to a 3D EM component is available whenever more accurate modeling is required.
A choice between non-matched or matched power detectors is driven by the context of a particular application. For the case of a matched detector, the simplest matching network topology is preferred where detector sensitivity is a must. However, the return loss values obtained by a simple network may not be sufficient for some applications. If this is the case, a more complex matching network must be designed trading-off the sensitivity for favorable return loss values. To accurately account for all the effects occurring within the matching network, use of electromagnetic modeling is highly recommended.
Modeling Wilkinson Combiner/Dividerat High Microwave Frequencies
A Wilkinson power combiner/divider is a three port microwave circuit frequently used as a building block for more complex circuits like amplifiers, mixers and antenna feeding networks. The simplest variant of the circuit performs equal amplitude and equal phase combining of two input signals. In well designed Wilkinson combiners, the isolation between the input ports at the operating frequency is substantial. A high isolation value is the basic motivation to implement the circuit in various applications. The circuit can be used in the opposite direction, i.e. for dividing an input signal in two equal amplitude and equal phase output signals.
In its simplest form, a circuit has a single section and performs two-way combining/dividing. Due to high demand for versatile combiner/divider components, numerous modifications of the basic circuit topology have been made in the past. These modifications include circuits performing combining/dividing with unequal amplitudes, multi-way signal combining/dividing, bandwidth extension by utilizing multisection topologies etc. Recently, much attention of the research community has been focused on suppression of a parasitic bandwidth occurring at the third harmonic of the operating frequency and operation in dual or multiple, non-harmonically related bands.
However, there are practical situations where even the design of basic, one section, two way combining/dividing structure can be very challenging. The typical example of such a situation is a design of Wilkinson combiner/divider at high microwave frequencies where the effects of discontinuities and component parasitics become significant.
This application note describes a practical aspect of designing a divider/combiner for high frequency of operation using powerful WIPL-D Microwave environment. It provides the step-by-step guide to accurately account for the effects occurring in a real-world circuit, make necessary trade-offs between important circuit performance and achieve first time right design.
Modeling with Analytic Schematic Elements
Figure 1. Schematic of the one section, two way microstripWilkinson combiner/divider in WIPL-D Microwave.
Figure 2. Simulated S parameters of schematic from Fig. 1.
Figure 3. Detailed schematic of microstrip Wilkinson combiner/dividerin WIPL-D Microwave including discontinuities andmounting pads of a resistor.
The schematic of the simplest, one section, two-way Wilkinson microstrip combiner/divider utilizing analytic elements from WIPL-D Microwave microstrip library is presented in Fig. 1. The circuit comprise two quarter wavelength transmission lines connected together directly at one end, and a resistor connected between the other ends of the transmission lines. For the case of equal amplitude combiner/divider in a 50 Ω system, a resistance of the resistor is 100 Ω, and the characteristic impedance of both transmission lines is 50 √2 Ω (~70.7 Ω). Due to the symmetry, equal amplitude, in-phase combining/dividing is automatically ensured. A section of 50 Ω transmission line is connected at each of the three ports. These lines are used to make connections with other circuits and do not influence the performance. A substrate chosen for this design has a relative dielectric constant value εr=3.5, and thickness h=0.254 mm. At the operating frequency of 24 GHz quarter wavelength line with characteristic impedance of 70.7 Ω is W=0.29 mm wide and L=1.98 mm long.
Simulated S parameters of Wilkinson combiner/divider presented in Fig. 1 are displayed in Fig. 2. All the ports are well matched with return loss values exceeding 25 dB in the frequency range 22-26 GHz. Isolation at the operating frequency is approximately 32 dB decreasing to approximately 25 dB at the band edges.
The schematic of the circuit shown in Fig. 1 is idealized, as it doesn’t address some important practical aspects a designer encounters when designing a real-world circuit. However, the S parameters presented in Fig. 2 can be regarded as a baseline for further discussion.
The first practical aspect that should be considered is providing conditions for a physical connection of a surface mounted device (SMD) resistor which is a preferred technology for the resistors in modern printed circuits. SMD resistors are available in different sizes which implies different dimensions of the pads required to attach (solder) the resistor in the circuit. For a particular resistor size chosen (0603) the recommended dimensions are WPad=0.5 mm for the width and LPad=0.3 mm for the length. Another practical aspect arising from the resistor connection is the necessity to divide continuous transmission line section of length L from Fig. 1 in two pieces, Ls and Lc, is, as illustrated in Fig. 3, where a detailed microstrip schematic of combiner/divider is presented. The schematic includes adequate models of all of the discontinuities occurring in the real-world combiner/divider microstrip circuit - an ideal wire connection preceding port 1 of Fig. 1 should be replaced with a T junction, right angle bends between Ls and Lc sections should be introduced, and dimensionless connections between the resistor and two transmission lines should be modeled with a microstrip T-junction.
Figure 4. Simulated S parameters of schematic from Fig. 3.
With the introduction of resistor connection details, the performance of the combiner/divider circuit changes. It was necessary to vary the length of the section Lc to recover the maximum isolation value at the operating frequency. The length Ls has been fixed to value of 0.2 mm. Optimum performance has been achieved with Lc=1.38 mm. Results after optimization are presented in Fig. 4. Due to the presence of the resistor pads and the discontinuities, the total length of the transmission lines is smaller than in the previous case. Moreover, the shape of the return loss curves is altered as the minima are shifted away from the operated frequency. However, the overall performance of the combiner/divider can still be regarded as very good as the return losses are better than 20 dB and isolation is better than 25 dB in the whole 22-26 GHz bandwidth.
Modeling with EM Component
It has been illustrated in the previous section that the performance of an ideal combiner/divider can be noticeably changed when more realistic model based on circuit analytical elements is introduced. WIPL-D Microwave design environment provides an additional tool to a designer to further explore the effects of non-idealities - the Wilkinson combiner/divider circuit can be modeled as an EM component. The EM component itself is presented in Fig. 5, while a circuit schematic used for analyzing the combiner/divider circuit is shown in Fig. 6. The results of the simulations are presented in Fig. 7-9.
Figure 5. EM component model of Wilkinsoncombiner/divider from Fig. 3.
Figure 6. WIPL-D Microwave schematic of Wilkinson combiner/dividerusing EM component from Fig. 5.
Figure 7. S parameters of schematic from Fig. 6 optimized for S11.
Figure 8. S parameters of schematic from Fig. 6 optimized for S22 and S33.
Figure 9. S parameters of schematic from Fig. 6 optimized for S32.
Analyzing S parameters presented in the figures, it becomes apparent that the performance of the combiner/divider as presented in Fig. 4 is not practically achievable. The circuit can be optimized either for one of the return losses, input or output, or for the isolation. The length of Lc section is considerably different for each of the case considered and is indicated in the figures. Additionally, a picture illustrating circuit layout is provided as an inset in each figure. These insets together with Fig. 5 best illustrate the basic reason for the significant influence of resistor connection to combiner/divider performance at high frequency of operation, which is the high ratio of the resistor pad length and width to the length Lc of a transmission line section. In other words, at high frequencies, resistor connection requires an area with a significant electrical length and width. That is the main reason for drastic change in performance comparing to the case of ideal connections presented in Fig. 1.
For Lc=1.42 mm input return loss has a minimum value of approximately 18 dB which is almost constant within the frequency band. On the other hand, a value for Lc of 1.0 mm provides almost constant return loss at ports 2 and 3 of approximately 30 dB. Depending on the particular application, one of the two return loss values might be a critical parameter in the design and a designer may opt to accept values of other S parameters and select the circuit design which provides a high return loss value required.
However, as pointed out earlier, the basic motivation to utilize the Wilkinson power combiner/divider is to provide high value for the isolation between ports 2 and 3, or otherwise much simpler Y junction structure can be used. Accordingly, a value of 1.57 mm for Lc, corresponding to the case presented in Fig. 9, is the best choice for most applications. The calculated isolation values are better than 40 dB at the central operating frequency decreasing to approximately 27 dB at the edges of the 22-26 GHz frequency band. It is interesting to notice that these values are higher than the ones found as an optimal for the schematic presented in Fig. 3. Such an outcome again signifies the limited accuracy of analytic models and the importance of electromagnetic analysis. Values of the return losses are approximately 15 dB within the band of interest, which makes the circuit viable for most applications.
Modeling SMD Resistor
Figure 10. Equivalent circuit of an SMD resistor.
In previous discussion SMD resistor has been represented solely as a resistance R. However, the physical construction of a resistor and the attachment to the pads both cause the effects that must be taken into account for accurate modelling. Equivalent circuit of an SMD resistor mounted on a printed circuit board (PCB) is presented in Fig. 10.
The parasitic effects introduced by resistor internal construction can be modeled with series inductance L and parallel capacitance C. Values of these elements are usually provided by a manufacturer. A connection to the pads adds a series inductance Lp and capacitance to ground Cg. Actual values of these quantities are dependent on εr and h of a substrate used for circuit fabrication, therefore they depend on the particular implementation. To a certain degree, modeling of the pads has already been introduced with EM component model from Fig. 5. However, to completely conform to the physical reality, the location of the reference plains for EM analysis should be aligned with the places of resistor connection, as demonstrated in Fig 11. A complete schematic used to analyze the combiner/divider circuit, including the modeling of 0603 size 100 Ω SMD resistor, is presented in Fig. 12.
Figure 11. Modified EM component with shifted reference planes ofSMD resistor connection.
Figure 12. Modified schematic of Wilkinson combiner/divider witha model of 100 Ω resistor.
Figure 10. Equivalent circuit of an SMD resistor.
Figure 10. Equivalent circuit of an SMD resistor.
The results of the simulation of the circuit from Fig. 12 with Lc=1.57 mm, i.e. as previously optimized for isolation, are presented in Fig. 13. It is evident that a very high isolation value of more than 40 dB from Fig. 9 has changed to an average value of approximately 15 dB. The return loss values are slightly changed as well with an average value of approximately 17 dB.
With the help of additional simulations in WIPL-D Microwave design environment, it has been found that the main reason for reduced isolation is due to the parasitics arising from the internal resistor construction. The contribution of the resistor reference plain alignment, in this particular case, has been found to be marginal having an impact in reducing an isolation value by 0.8 dB.
To recover a high isolation value, an optimization of the schematic from Fig. 12 has been performed resulting in the optimal performance as presented in Fig. 13. The optimum isolation value of approximately 22 dB has been achieved with Lc=0.95 mm. As a final remark, it should be emphasized that it is of crucial importance to tightly control resistor placement during fabrication, or otherwise the performance of the circuit could easily move away from the one presented in Fig. 14.
The accurate modeling of the effects occuring at high microwave frequencies is the key to successful design of a Wilkinson power combiner/divider. WIPL-D Microwave provides a complete environment required for a design of these circuits including circuit and electromagnetic co-simulation.
Example of a design cycle has been provided. Thecycle starts with the analysis of an ideal, by-the-book circuit schematic, continues to a more detailed schematic with models for microstrip discontinuities, and is then further expanded with the introduction of an EM component to model a complete microstrip circuit with high accuracy. Finally, the impact of a real-world resistor is demonstrated. The impact of each modeling step to degradation of circuit performance comparing to an ideal circuit is illustrated and explained in details. A designer is therefore provided with a clear understanding of what to expect and how to mitigate the potential problems at early stages of the design - it will be a good practice to utilize the smallest resistor size avaialbe, and, if possible, pick a substrate so that line-to-resistor-pad length ratio is maximized.